USB flash memory device with integrated USB controller

ABSTRACT

A storage unit made of flash array and a USB controller, is implemented to be compatible with then USB specification. The unit includes memory modules which can accept write commands and read commands and are erasable and non-volatile herein referred to as flash modules. The USB/flash controller is configured to provide USB functionality and compatibility alone with common flash operations such as programming reading and erasing the above mentioned components.A USB flash memory device includes at least one flash memory module, a USB connector, a USB controller, and an identification structure for holding memory size and manufacturing type information of the flash memory module. The USB controller is configured to send and receive USB-defined data packets to or from a host via the USB connector, to extract operation codes and logical addresses from the USB-defined data packets, and to carry out at least one of reads, writes and erases in the flash memory module in accordance with the USB-defined data packets, and to interpret the operation codes into corresponding commands. The USB controller is configured to activate a respective memory technology driver in accordance with the memory size and manufacturing type information in the identification structure. The activated memory technology driver is configured to perform the commands on the flash memory module corresponding to the logical addresses.

RELATED APPLICATIONS

This application is a continuation reissue application of reissueapplication Ser. No. 10/292,868, filed Nov. 13, 2002 now U.S. Pat. No.Re. 42,443, which is a reissue application of U.S. Ser. No. 09/285,706,filed on Apr. 5, 1999, now U.S. Pat. No. 6,148,354, issued on Nov. 14,2000.

More than one reissue application has been filed for the reissue of U.S.Pat. No. 6,148,354. The reissue applications are application Ser. No.10/292,868, filed Nov. 13, 2002, now U.S. Pat. No. Re. 42,443, issued onJun. 7, 2011; application Ser. No. 10/293,986, filed Nov. 14, 2002, nowU.S. Pat. No. Re. 42,397, issued on May 24, 2011; application Ser. No.13/005,501, titled “USB Flash Memory Device with Integral MemoryTechnology Driver,” filed Jan. 12, 2011, and application Ser. No.13/005,505, (the present application), filed Jan. 12, 2011, all of whichare reissues of U.S. Pat. No. 6,148,354 and are hereby incorporated byreference in their entirety.

FIELD AND BACKGROUND OF THE INVENTION

The present invention is related to semiconductor memory devices, and inparticular to erasable and programmable nonvolatile memory modules whichare connected to a host platform using the USB PC Bus.

Erasable and programmable non-volatile memory modules, hereinafterreferred to as flash memory or flash devices, are known in the art forstorage of information. Flash devices include electrically erasable andprogrammable read-only memories (EEPROMs) made of flash-type,floating-gate transistors and are non-volatile memories similar infunctionality and performance to EPROM memories, with an additionalfunctionality that allows an in-circuit, programmable, operation toerase pages of the memory. One example of an implementation of such aflash device is given in U.S. Pat. No. 5,799,168, incorporated byreference as if fully set forth herein.

Flash devices have the advantage of being relatively inexpensive andrequiring relatively little power as compared to traditional magneticstorage disks. However, in a flash device, it is not practical torewrite a previously written area of the memory without a preceding pageerase of the area. This limitation of flash devices causes them to beincompatible with typical existing operating system programs, since datacannot be written to an area of memory within the flash device in whichdata has previously. been written, unless the area is first erased. Asoftware management system, such as that disclosed in U.S. Pat. No.5,404,485, filed on Mar. 5, 1993, which is incorporated as if fully setforth herein, is required to manage these functions of the flash memorydevice.

Currently, these flash memory devices have a second limitation, which isthat they must be either attached statically to the host platform, orattached and detached dynamically using the PCMCIA [Personal ComputerMemory Card International Association] interface. Both implementationshave drawbacks, including difficulty of use and high cost.

A more useful implementation would follow the USB standard, as describedin the USB Specification Version 1.1 which is incorporated as if fullyset forth herein. The USB standard offers a smaller form factor andgreater ease of use for the end user, while lowering the cost of theimplementation. This standard is specified to be an industry-widestandard promoted by companies such as Compaq Computer Corporation,Microsoft, IBM and Intel to serve as an extension to the PC architecturewith a focus on Computer Telephony Integration (CTI), the consumer, andproductivity applications.

The criteria which were applied to define the architecture for the USBstandard include the ease of PC (personal computer) peripheralexpansion, low cost, support of transfer rates up to 12 Mb/second andfull support for real-time data, voice, audio, and compressed video.This standard also offers protocol flexibility for mixed-modeisochronous data transfers and asynchronous messaging, integration incommodity device technology and provision of a standard interface forrapid integration into any given host product. In addition, the USBstandard represents a single model for cabling and attaching connectors,such that all of the details of the electrical functions, including busterminations, are isolated from the end user. Through the standard, theperipheral devices are self-identifying, and support automatic mappingof functions to a driver. Furthermore, the standard enables allperipheral devices to be dynamically attachable and re-configurable.

A system constructed according to the USB standard is described by threeseparate, defined areas: USB interconnection, USB devices and the USBhost platform. The USB interconnection is the manner in which USBdevices are connected to, and communicate with, the host platform. Theassociated functions and components include the bus topology, which isthe connection model between USB devices and the host platform.

The USB physical interconnection has a tiered star topology. A hub is atthe center of each star. Each wire segment is a point-to-pointconnection between the host platform and a hub or function, or a hubconnected to another hub or function.

In terms of a capability stack, the USB tasks which are performed ateach layer in the system include a data flow model and a schedule. Adata flow model is the manner in which data moves in the system over theUSB between data producers and data consumers. A schedule determinesaccess to the interconnection, which is shared. Such scheduling enablesisochronous data transfers to be supported and eliminates arbitrationoverhead.

The USB itself is a polled bus. The host controller on the host platforminitiates all data transfers. All bus transactions involve thetransmission of up to three packets. Each transaction begins when thehost controller, on a scheduled basis, sends a USB packet describing thetype and direction of transaction, the USB device address, and endpointnumber. This packet is referred to as the “token packet.” The USBdevice, to which the packet is addressed, selects itself by decoding theappropriate address fields. In a given transaction, data is transferredeither from the host platform to a device or from a device to the hostplatform. The direction of data transfer is specified in the tokenpacket. The source of the transaction then sends a data packet orindicates that the source has no data to transfer. The destination, ingeneral, responds with a handshake packet indicating whether thetransfer was successful.

The USB data transfer model between a source and destination on the hostplatform and an endpoint on a device is referred to as a “pipe”. Thereare two types of pipes: stream and message. Stream data has noUSB-defined structure, while message data does. Additionally, pipes haveassociations of data bandwidth, transfer service type, and endpointcharacteristics like directionality and buffer sizes. Most pipes comeinto existence when a USB device is configured. One message pipe, thedefault control pipe, always exists once a device is powered, in orderto provide access to the configuration, status, and control informationfor the device.

The transaction schedule for the USB standard permits flow control forsome stream pipes. At the hardware level, this prevents situations inwhich buffers experience underrun or overrun, by using a NAK handshaketo throttle the data rate. With the NAK handshake, a transaction isretried when bus time is available. The flow control mechanism permitsthe construction of flexible schedules which accommodate concurrentservicing of a heterogeneous mix of stream pipes. Thus, multiple streampipes can be serviced at different intervals with packets of differentsizes.

The USB standard, as described, has three main types of packets,including token packets, data packets and handshake packets. An exampleof each type of packet is shown in background art FIGS. 1-3. Backgroundart FIG. 4 shows an exemplary USB abstract device.

A token packet 10, as shown in background art FIG. 1, features a PID(packet identification) field 12, specifying one of three packet types:IN, OUT, or SETUP. If PID field 12 specifies the IN packet type, thedata transaction is defined from a function to the host platform. If PIDfield 12 specifies the OUT or SETUP packet type, the data transaction isdefined from the host platform to a function.

An ADDR field 14 specifies the address, while an ENDP field 16 specifiesthe endpoint for token packet 10. For OUT and SETUP transactions, inwhich PID field 12 specifies that token packet 10 is an OUT packet typeor a SETUP packet type, ADDR field 14 and ENDP field 16 uniquelyidentify the endpoint for receiving the subsequent data packet, shown inFIG. 2, which follows after token packet 10. For IN transactions, inwhich PID field 12 specifies that token packet 10 is an IN packet type,ADDR field 14 and ENDP field 16 uniquely identify which endpoint shouldtransmit a data packet. A CRC5 field 18 contains the checksum, fordetermining that token packet 10 has been received without corruption.Only host platform can issue token packets 10, such that token packets10 provide control over transmission of the subsequent data packets.

As shown in background art FIG. 2, a background art USB data packet 20also features a PID (packet identification) field 22 for identifying thetype of data packet. Data packet 20 also features a data field 24 foroptionally. containing data, and a CRC field 26 for containing thechecksum as previously described.

Background art FIG. 3 shows a background art USB handshake packet 28,which features only a PID (packet identification) field 30. Handshakepackets 28 are used to report the status of a data transaction and canreturn values indicating successful reception of data, commandacceptance or rejection, flow control, and halt conditions. Onlytransaction types which support flow control can return handshakepackets 28. Handshake packets 28 are always returned in the handshakephase of a transaction and may be returned, instead of data packets 20,in the data phase of a transaction.

These three different types of packets are exchanged during variousphases of the transaction which includes a USB device. A schematic blockdiagram of the functional blocks in a typical USB device 32 is shown inFIG. 4 for an abstract background art USB device. USB device 32typically includes a USB electrical interface 34, featuring a cable anda connector, which is a physical interface for receiving andtransmitting electrical signals which are compatible with the USBspecification as previously described. The signals are then passed to alogical interface 36, which includes one or more buffers, the deviceaddress decoder for decoding the address of the source device for thesignals, and a SYNC field synchronizer for synchronizing the signals.Information and structures required for management of USB abstractdevice 32 as a USB device are stored in a USB class control andenumeration engine 38. A function and device engine 40, also termed the“application”, controls and manages the specific functions andproperties of USB abstract device 32. In addition, function and deviceengine 40 also consumes and produces most of the data over the USB bus.

The USB specification does not define the relationship between differententities in USB abstract device 32, however. Rather, the USBspecification describes only the requirements for the packets, and forthe electrical and physical connection between USB abstract device 32and the bus. Therefore the connections and relationships shown inbackground art FIG. 4 are only one example of an implementation whichfulfills the requirements of the USB specification. Thus, any specificdevice for fulfilling the USB specification must have a specificallydefined and described architecture.

Unfortunately, no such architecture exists for a flash memory devicecontaining one or more flash memory modules, which would enable theflash memory device to connect to a bus defined according to the USBspecification and thereby to form part of a USB system on a hostplatform. For example, U.S. Pat. No. 5,799,168 does not teach or suggestsuch an implementation for the flash device. As mentioned previously,such an architecture would be particularly useful for a number ofreasons, including low cost, ease of use and transparency to the enduser.

There is thus a need for, and it would be useful to have, anarchitecture for defining and describing a flash memory device which iscompatible with a USB system and which follows the USB specification,such that the flash memory device could sit on a USB-defined bus andcommunicate with the host platform through this bus.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a background art USB token packetstructure;

FIG. 2 is a schematic block diagram of a background art USB data packetstructure;

FIG. 3 is a schematic block diagram of a background art USB handshakedata packet structure;

FIG. 4 is a schematic block diagram of an exemplary background art USBdevice;

FIG. 5 is a schematic block diagram of a system with a flash USB devicefunctionality according to the present invention;

FIG. 6 is a schematic block diagram of the USB Flash disk;

FIG. 7 is a schematic block diagram of a flash identification requestpacket;

FIG. 8 is a schematic block diagram of a flash identification statuspacket;

FIG. 9 is a schematic block diagram of a flash write request packet;

FIG. 10 is a schematic block diagram of a flash write status packet;

FIG. 11 is a schematic block diagram of a flash read request packet;

FIG. 12 is sa schematic block diagram of a flash read status packet;

FIG. 13 is a schematic block diagram of a flash erase request packet;and

FIG. 14 is a schematic block diagram of a flash erase status packet.

SUMMARY OF THE INVENTION

The present invention is of a flash memory device, containing one ormore flash modules, in which the flash memory is mapped to the addressspace of an ASIC or a controller which has a USB-defined electricalinterface and a USB-defined logical interface. This controller/ASIC(hereinafter termed a “controller”) supports the USB functionalityaccording to the USB standard, thereby supporting enumeration onto theUSB bus, as well as data reception and transmission over USB pipes toand from USB endpoints. This controller also supports the functionalityand control of the flash memory device, as well as the processing ofcommand and data packets from the host controller. The host controlleruses one of several possible protocols, either standard or proprietary,to signal the next command to be performed to the USB flash controller.Thus, the entire device acts as a dynamically attachable/detachablenon-volatile storage device for the host platform.

According to the present invention, there is provided a USB flash memorydevice for connecting to a USB-defined bus, the flash memory devicecomprising: (a) at least one flash memory module for storing data; (b) aUSB connector for connecting to the USB-defined bus and for sendingpackets on, and for receiving packets from, the USB-defined bus; and (c)a USB controller for controlling the at least one flash memory moduleand for controlling the USB connector according to at least one packetreceived from the USB-defined bus, such that data is written to and readfrom the at least one flash memory module.

Hereinafter, the term “computer” includes, but is not limited to,personal computers (PC) having an operating system such as DOS,Windows™, OS/2™ or Linux; Macintosh™ computers; computers havingJAVA™-OS as the operating system; and graphical workstations such as thecomputers of Sun Microsystems™ and Silicon Graphics™, and othercomputers having some version of the UNIX operating system such as AIX™or SOLARIS™ of Sun Microsystems™; or any other known and availableoperating system, including operating systems such as Windows CE™ forembedded systems, including cellular telephones, handheld computationaldevices and palmtop computational devices, and any other computationaldevice which can be connected to a network. Hereinafter, the term“Windows™” includes but is not limited to Windows95™, Windows 3.X™ inwhich “x” is an integer such as “1”, Windows NT™, Windows98™, WindowsCE™ and any upgraded versions of these operating systems by MicrosoftInc. (Seattle, Wash., USA).

DETAILED DESCRIPTION OF THE INVENTION

The present invention is of a flash memory device, containing one ormore flash modules, in which the flash memory is mapped to the addressspace of an ASIC or a controller which has a USB-defined electricalinterface and a USB-defined logical interface. This controller/ASIC(hereinafter termed a “controller”) supports the USB functionalityaccording to the USB standard, thereby supporting enumeration onto theUSB bus, as well as data reception and transmission over USB pipes toand from USB endpoints. This controller also supports the functionalityand control of the flash memory device, as well as the processing ofcommand and data packets from the host controller. The host controlleruses one of several possible protocols, either standard or proprietary,to signal the next command to be performed to the USB flash controller.Thus, the entire device acts as a dynamically attachable/detachablenon-volatile storage device for the host platform.

While the invention is susceptible to various modifications and can beimplemented using many alternative forms, the embodiment is shown by wayof example in the drawings and will be described in details in thefollowing pages. It should be understood that one of ordinary skill inthe art appreciates that the present invention could be implemented invarious other ways. The intention is to cover all modifications andalternatives falling within the spirit of the current invention.

The principles and operation of a USB flash device and system accordingto the present invention may be better understood with reference to thedrawings and the accompanying description, it being understood thatthese drawings are given for illustrative purposes only and are notmeant to be limiting.

Referring now to the drawings, FIG. 5 is a schematic block diagram ofthe main components of a flash memory device and system according to thepresent invention. A flash memory system 42 includes a host platform 44as shown. Host platform 44 operates USB flash device 46 as anon-volatile storage space.

Host platform 44 is connected to USB flash device 46 according to thepresent invention through a USB cable 48. Host platform 44 connects toUSB cable 48 through a USB host connector 50, while USB flash device 46connects to USB cable 48 through a USB flash device connector 52. Hostplatform 44 features a USB host controller 54 for controlling andmanaging all USB transfers on the USB bus.

USB flash device 46 features a USB flash device controller 56 forcontrolling the other components of USB flash device 46 and forproviding an interface for USB flash device 46 to the USB bus, USB flashdevice connector 52 and at least one flash memory module 58. Flashmemory module 58 is preferably an array of flash memory modules 58 inwhich the data is stored.

Whenever USB flash device 46 becomes connected to host platform 44, astandard USB enumeration process takes place. In this process hostplatform 44 configures USB flash device 46 and the mode of communicationwith USB flash device 46. Although there are many different methods forconfiguring USB flash device 46, for the purposes of clarity only andwithout intending to be limiting, the present invention is explained ingreater detail below with regard to a method in which host platform 44issues commands and requests to USB flash device 46 through oneendpoint. Host platform 44 queries USB flash device 46 through the otherendpoint for status changes, and receives related packets if any suchpackets are waiting to be received.

Host platform 44 requests services from USB flash device 46 by sendingrequest packets to USB host controller 54. USB host controller 54transmits packets on USB cable 48. These requests are received by USBflash device controller 56 when USB flash device 46 is the device on theendpoint of the request. USB flash device controller 56 then performsvarious operations such as reading, writing or erasing data from or toflash memory module(s) 58, or supporting basic USB functionality such asdevice enumeration and configuration. USB flash device controller 56controls flash memory module(s) 58 by using a control line 60 to controlthe power of flash memory module(s) 58, and also through various othersignals such as chip enable, and read and write signals for example.Flash memory module(s) 58 are also connected to USB flash devicecontroller 56 by an address/data bus 62. Address/data bus 62 transferscommands for performing read, write or erase commands on flash memorymodule(s) 58, as well as the addresses and data for these commands asdefined by the manufacturer of flash memory module(s) 58.

In order for USB flash device 46 to notify host platform 44 on theresult and status for different operations requested by host platform44, USB flash device 46 transmits status packets using the “status endpoint”. According to this procedure, host platform 44 checks (polls) forstatus packets and USB flash device 46 returns either an empty packet ifno packets for new status messages are present, or alternatively returnsthe status packet itself.

A more detailed structure of the functional components of USB flashdevice 46 is shown in FIG. 6. USB flash device 46 includes the physicaland electrical interface defined for the USB standard, shown here as USBflash device connector 52 and a connector interface 64. USB flash deviceconnector 52 receives the electrical signals from USB cable 48 whichcarries electrical signals from host controller (not shown). Thesesignals are then passed through connector interface 64. Everymillisecond, a USB frame is carried on the USB-defined bus, such thatpackets could be sent to USB flash device 46.

Connector interface 64 then receives these packets through a firstinterface component, which is a combined physical and logical interface66. A functional interface 68 is specifically designed to receive tokenpackets as defined in the USB specification and as previously describedwith regard to FIG. 1. These token packets are related only toparticular functional aspects of USB flash device 46 which are requiredfor the USB standard, and do not have any relation to particularapplication of USB flash device 46 as a flash disk according to thepresent invention. These token packets and their respective returneddata packets enable USB host controller 54 (not shown) and host platform44 (not shown) to identify USB flash device 46 and allocate resourcesfor USB flash device 46 on the USB bus. Thus, functional interface 68only supports USB functionality needed for the identification andregistration of USB flash device 46 on the USB bus.

USB flash device 46 also features an application packet extractor 70which extracts the application data and commands from the USBapplication packets, such that application packet extractor 70 supportsonly application related packets. Next, any requests to USB flash device46 by host platform 44 (not shown), in the form of read, write, identifyand erase commands, are interpreted by an application commandinterpreter 72. For any commands which involve data or an address, suchas read, write and erase commands, an address resolve module 74translates the address from the logical address space to the physicaladdress space. Host platform 44 (not shown) relates to a linear addressspace of logical addresses, while USB flash device 46 contains at leastone, and preferably a plurality of, flash modules 58, each of which hasa physical address space. Thus, a translation must be performed betweenthe logical address space of host platform 44 (not shown) and physicaladdress space or spaces of USB flash device 46. There are many ways toimplement such a translation which are suitable for the presentinvention. One example of a suitable implementation of an addresstranslation method is described with regard to U.S. Pat. No. 5,404,485,previously incorporated by reference as if fully set forth herein, whichteaches a method for managing a flash memory as a flash disk and whichis suitable for operation with the present invention.

A data handler 76 handles data related aspects of any received commands,and conveying the data through functional interface 68 to and from flashmodule(s) 58. Optionally and preferably, data handler 76 performs anyerror correction and detection methods. Application command interpreter72, data handler 76 and address resolve module 74 all operate with anunderlying Memory Technology Driver (MTD) 78 to write, read or erase aparticular flash module 58 and the desired address on that flash module58.

Host platform 44 checks for status changes in USB flash device 46 andreads status packets from USB flash device 46 when a new status packetis available. Using these status packets, USB flash device 46 cantransmit, to host platform 44, the results of different commands issuedby host platform 44 in its requests (not shown). For example, the readcommand status packet contains one of the available status words such as“success”, “error” or “invalid address”, which enables host-platform 44to determine the result of the read command (not shown). Similarly, theerase status packet contains a status word indicating the completion ofthe erase process. A write status packet is used by USB flash device 46to notify host platform 44 about the result of the write command, forexample whether the command was successful or erroneous, and whether USBflash device 46 is ready for additional write requests from hostplatform 44.

A Memory Technology Driver, or MTD 78 typically contains routines toread, write and erase the flash memory device controlled by thecontroller operating MTD 78. In addition, MTD 78 optionally contains anidentification routine for recognizing the proper type of flash memorydevice for which MTD 78 was designed, so that the controller candetermine which MTD should be activated upon interacting with aparticular flash memory device array. In addition, an identificationroutine should be able to detect the size of the array of flash memorydevices, including the number of flash memory devices within the array,and various features of the flash array geometry, such as interleavingand bus width. This information later enables host platform 44 platformto determine the address space and size of the storage media. U.S. Pat.No. 5,799,168, previously incorporated by reference, discloses anexample of such an MTD for a flash device.

Using the above described protocol and architecture, host platform 44can optionally implement any application which is implementable with anyregular memory mapped or I/O mapped flash memory device. For example,host platform 44 can give a standard block device interface to eachapplication, such as a magnetic storage medium “hard disk” drive, asdisclosed in the previously described U.S. Pat. No. 5,404,485.

As an example of a preferred embodiment of the present invention, theoperation of a host system connected to a USB flash device according tothe present invention is described with regard to the processes ofidentifying, programming, reading and erasing the flash device. For thepurposes of illustration only and without intending to be limiting inany way, the exemplary USB flash device has an array of two flash memorymodules, each of which is 64 Mbit in size. The address translation tableis within the flash device so that host platform operates with logicaladdresses. All commands and return codes between the flash device andthe host platform are carried on USB data packets, and are transferredthrough USB data pipes. The exact structure of the packets, pipes andtimings are described in the USB specification.

The operation of the exemplary device and system according to thepresent invention is as follows. When the USB flash device is firstconnected to the host platform, the USB host controller assigns anaddress to the USB flash device on the USB bus, and also assignsresources as described in the USB specification. The USB flash deviceactually asks the host platform to assign these resources, and mustinform the host platform how much of these resources are needed. Thus,the USB flash disk can optionally support slower device speeds if theUSB host platform has already allocated resources to other devices.

The USB controller also negotiates with the flash modules and determinesthe size and manufacturing type of these modules. The controller thenbuilds an identification structure holding this information, as well asthe translation table and logical address space.

After the USB host controller identifies the USB flash device, the hostplatform often uploads a USB client driver. The driver issues anidentification request command to the USB host controller, causing thecontroller to transmit an identification data packet 80, shown in FIG.7. Identification packet 80 contains PID field 22 and checksum field 26,as described previously for background art FIG. 2. Identification packet80 also contains an “identify” operation code in an operation code field82. The packet extractor of the USB flash device receives identificationdata packet 80 and transfers the operating code of the “identify”command to the application command interpreter.

In response to the “identify” command, the flash device then sends anidentification data packet 84, shown in FIG. 8. In addition to thefields shown in FIG. 7, identification data packet 84 also containsinformation about the size of the flash device in a flash device sizefield 86, as well as information about the size of the minimal eraseunit for erasing the flash memory in an erase unit size field 88.

All of the packets described in this example are only data packets whichare sent on the USB bus. Before each data packet is sent, a USB tokenpacket is transmitted, instructing the USB controller as to the identityof the device end point to which the data packet should be transmitted.Upon successful reception of the packet, the USB controller issues a USBACK packet as described in the USB specification.

Once the device drivers in the host platform receive this status packet,the drivers can start issuing read and write commands to the USB flashdevice with the application commands. When a write request is sent, aUSB data packet with the operation code for the “write” command, and thebuffer containing the data, is transferred to the USB flash device. Awrite data packet 90 is shown in FIG. 9, which again includes the fieldsshown previously in FIG. 8, except that write data packet 90 alsoincludes a write field 92 with the “write” operational code; an ADDRfield 94 with the logical address to be written; a LEN field 96 with thelength to be written; and a DATA field 98 which contains the actual datato write. The packet extractor extracts the operational code from writedata packet 90 and transfers this code to the application commandinterpreter. The logical address is transferred to the address resolvemodule which translates this logical address to a physical address onone of the flash modules. The data handler optionally calculates errorcorrection and detection mechanisms if employed by the USB flash device.Once all of the flash memory modules are ready, a “write” command issent to the flash module or modules containing the physical address,which may optionally span across more than one flash module to the MTDblock. The MTD block then issues a “write” command on the data/addressbus which connects the flash modules to the USB device controller. Oncethe operation is complete and a status packet is returned to the MTD,the result of the operation is transmitted to the host controller andpassed to the device driver in the host platform.

When the flash controller finishes the writing process, the controllersignals to the host platform that the status of the USB flash memorydevice has changed, by sending a “write status” packet 100, as shown inFIG. 10. In place of data field 98, write status packet 100 contains astatus field 102. The host platform reads the status packets from theflash memory device, and from write status packet 100, the host platformretrieves information on the completion status of the write command byreading status field 102. In this example, the flash memory devicerepeats ADDR field 94 and LEN field 96 in order for the host platform tohave a reference to the specific command related to status packet 100.

As shown in FIG. 11, a “read request” packet 104 contains the operationcode for the “read” command in a read field 106, and the logical addressof the desired location from which the flash controller should read inan ADDR field 108. Upon receiving this command, the flash controllerissues a read command to the MTD block, after the address resolve modulehas translated the address contained in ADDR field 108 to a specificphysical address in one of the flash components.

When the flash controller receives the data from the flash device,either after the read command was issued, or if an error occurred, theflash controller sends a signal to the host platform to indicate that anew status packet must be read. The host platform issues a read requestand receives a “read status” packet 110 as shown in FIG. 12. Read statuspacket 110 contains the address of the read data in ADDR field 108, aswell as the length of the read data in a LEN field 112 and the dataitself in a data field 114. Read status packet 110 also features thestatus word, according to which the operation was completed, in a statusfield 116. The read operation can be completed with many differentstatus situations such as success, fail, error detected, invalidaddress, invalid length and so forth.

When the host platform needs to erase an erase unit in the flash device,the host platform issues an “erase request” packet 118, shown in FIG.13. This packet contains the “erase” operation code in an erase field120, and the logical address of the erase unit in an ADDR field 122.Upon receiving such a request, the flash controller translates thelogical address to a physical erase unit address on one of the physicaladdress spaces of the flash modules, and issues an erase command to theMTD block.

The erase process generally takes more time then a read or writeprocess. When this erase process is finished, the controller notifiesthe host platform a new status packet is ready to transmit. Thecontroller then transmits an “erase status” packet 124, as shown in FIG.14. Erase status packet 124 contains the address of the erased unit inADDR field 122, thereby providing the host platform with a reference tothe erase requests. The status according to which the operation wascompleted is provided in a status field 126.

It will be appreciated that the above descriptions are intended only toserve as examples, and that many other embodiments are possible withinthe spirit and the scope of the present invention.

What is claimed is:
 1. A USB flash memory device for connecting to aUSB-defined bus, the flash memory device comprising: (a) at least oneflash memory module for storing data; (b) a USB connector for connectingto the USB-defined bus and for sending packets on, and for receivingpackets from, the USB-defined bus; (c) a USB controller for controllingsaid at least one flash memory module and for controlling said USBconnector according to at least one packet received from the USB-definedbus, such that data is written to and read from said at least one flashmemory module; (d) an electrical interface for connecting to said USBconnector and for receiving said packets from said USB connector as aplurality of electrical signals; (e) a logical interface for connectingto said electrical interface and for translating said plurality ofelectrical signals to logic signals, said logic signals being passed tosaid at least one flash memory module; (f) a functional interface forreceiving said logic signals such that if said logic signals represent aUSB functional packet, said functional interface sends a USB command tosaid USB controller according to said USB functional packet; (g) anapplication packet extractor for connecting to said logical interfaceand for receiving said logic signals, said application packet extractorextracting at least one packet from said logic signals; and (h) anapplication command interpreter for receiving said at least one packetand for determining a command according to said at least one packet,said command being passed to said USB controller.
 2. The flash memorydevice of claim 1, further comprising: (i) an address resolver modulefor receiving said at least one packet and for resolving an addresscontained in said at least one packet, said address being sent to saidUSB controller, such that said command is performed according to saidaddress.
 3. The flash memory device of claim 2, wherein said command isa write command for writing data to said at least one flash memorymodule and said address is a logical address for writing said data, suchthat said address resolver module resolves said logical address to aphysical address of said at least one flash memory module.
 4. The flashmemory device of claim 2, wherein said command is a read command forreading data from said a least one flash memory module and said addressis a logical address for reading said data, such that said addressresolver module resolves said logical address to a physical address ofsaid at least one flash memory module.
 5. The flash memory device ofclaim 2, further comprising: (j) a data handler for performing an errordetection and correction routine for said at least one flash memorymodule.
 6. The flash memory device of claim 5, further comprising: (k) astatus handler for receiving said USB functional packet from saidfunctional interface, and for sending a status packet concerning astatus of said at least one flash memory module according to said USBfunctional packet.
 7. The flash memory device of claim 6, furthercomprising: (l) a MTD (memory technology driver) for receiving a writecommand and physical address of said at least one flash memory module,and for performing said write command to said physical address.
 8. A USBflash memory device for connecting to a USB-defined bus the flash memorydevice comprising: at least one flash memory module; a USB connectoradapted for connection to a USB-defined bus; and a USB controllerconfigured to interface with a host via the USB-defined bus, to send andreceive USB-defined packets, including USB-defined data packets, via theUSB connector to or from the host, and to manage memory reads, writesand erases in the at least one flash memory module in accordance withthe USB-defined data packets, wherein the USB controller includes: apacket extractor to extract operation codes and logical addresses fromthe USB-defined data packets; a command interpreter which is adapted tointerpret the operation codes into commands corresponding to one of thememory reads, writes and erases; and an address resolver module adaptedfor converting the logical addresses into corresponding physicaladdresses in one or more of the at least one flash memory module.
 9. TheUSB flash memory device according to claim 8, further comprising: amemory technology driver for receiving the commands from the commandinterpreter and the physical addresses from the address resolver moduleand for performing the commands to memory cells of the at least oneflash memory module identified by the physical addresses.
 10. The USBflash memory device according to claim 9, wherein, if one of thecommands is a write command for writing data associated with arespective logical address, the address resolver module is configured toconvert the respective logical address into a physical address of the atleast one flash memory module and the memory technology driver isconfigured to write the data to memory cells of the at least one flashmemory module identified by the physical address.
 11. The USB flashmemory device according to claim 9, wherein, if one of the commands is aread command for reading data associated with a respective logicaladdress, the address resolver module is configured to convert therespective logical address into a physical address of the at least oneflash memory module and the memory technology driver is configured toretrieve the data from memory cells of the at least one flash memorymodule identified by the physical address.
 12. The USB flash memorydevice according to claim 8, wherein the USB controller is implementedas a single integrated circuit.
 13. The USB flash memory deviceaccording to claim 8, wherein the USB controller is configured tonegotiate with the at least one flash memory module to determine atleast one of a size of the at least one flash module and a manufacturingtype of the at least one flash module.
 14. The USB flash memory deviceaccording to claim 13, wherein the USB controller is configured tonotify the host that it is ready for use after the negotiation.
 15. TheUSB flash memory device according to claim 13, wherein the USBcontroller is configured to use the determined size and manufacturingtype to build an address translation table.
 16. The USB flash memorydevice according to claim 8, wherein the flash memory device isconfigured to act as a dynamically attachable/detachable non-volatilestorage device for the host.
 17. The USB flash memory device accordingto claim 8, wherein the at least one flash memory module comprises aplurality of flash memory modules.
 18. The USB flash memory deviceaccording to claim 17, wherein the USB controller includes a pluralityof chip enable signal lines for attaching to the plurality of flashmemory modules.
 19. A data-processing method performed by a USB flashmemory device, wherein the USB flash memory device includes at least oneflash memory module, a USB controller, and a USB connector adapted foroperatively coupling the at least one flash memory module and the USBcontroller to a host via a USB-defined bus, the method comprising:receiving USB-defined packets from the host via the USB-defined bus andthe USB connector, wherein the USB-defined packets include one or moreUSB-defined data packets; under the control of the USB controller:extracting operation codes and logical addresses from the USB-defineddata packets; interpreting the operation codes into commandscorresponding to one of memory reads, writes and erases; converting thelogical addresses into corresponding physical addresses in one or moreof the at least one flash memory module; performing the commands tomemory cells within the at least one flash memory module identified bythe physical addresses.
 20. The data-processing method according toclaim 19, further comprising: under the control of the USB controller:determining memory size and manufacturing type information of the atleast one flash memory module; building an address translation table inaccordance with the determined memory size and manufacturing typeinformation; and converting the logical addresses into the physicaladdresses of the at least one flash memory module using the addresstranslation table.
 21. The data-processing method according to claim 20,further comprising: storing the memory size and manufacturing typeinformation in an identification structure of the USB controller. 22.The data-processing method according to claim 19, further comprising:activating a memory technology driver in accordance with typeinformation of the at least one flash memory module, wherein the memorytechnology driver is configured to receive the commands and the physicaladdresses and perform the commands to memory cells of the at least oneflash memory module identified by the physical addresses.
 23. Thedata-processing method according to claim 22, wherein the memorytechnology driver is configured to: receive from the USB controller awrite command, a predefined amount of data, and a physical address ofthe at least one flash memory module; and write the predefined amount ofdata into memory cells within the at least one flash memory modulecorresponding to the physical address in accordance with the writecommand.
 24. The data-processing method according to claim 22, whereinthe memory technology driver is configured to: receive from the USBcontroller a read command and a physical address of the at least oneflash memory module; and retrieve data from memory cells within the atleast one flash memory module corresponding to the physical address inaccordance with the read command.
 25. The data-processing methodaccording to claim 22, wherein the memory technology driver isconfigured to: receive from the USB controller an erase command and aphysical address of the at least one flash memory module; and erase datain memory cells within the at least one flash memory modulecorresponding to the physical address in accordance with the erasecommand.
 26. The data-processing method according to claim 19, furthercomprising: under the control of the USB controller, negotiating withthe at least one flash memory module to determine at least one featureof the at least one flash memory module.
 27. The data-processing methodaccording to claim 26, further comprising: under the control of the USBcontroller, notifying the host after its negotiation with the at leastone flash memory module.
 28. The data-processing method according toclaim 19, further comprising: receiving electrical signals from the hostvia the USB-defined bus and the USB connector, wherein the electricalsignals are USB-compatible; and extracting the USB-defined packets fromthe electrical signals.
 29. A USB flash memory device for connecting toa USB-defined bus, the flash memory device comprising: (a) at least oneflash memory module; (b) a USB connector adapted for connection to aUSB-defined bus and for conveying USB-defined packets sent to orreceived from a host via the USB-defined bus; and (c) a USB controlleradapted to communicate with the host over the USB-defined bus via theUSB connector and to manage the at least one flash memory module inaccordance with the USB-defined packets, including for carrying outread, write and erase actions, wherein the USB controller comprises aUSB-defined electrical and logical interface coupled to the USBconnector for transferring the USB-defined packets, a packet extractorfor receiving USB-defined data packets via the USB-defined electricaland logical interface and extracting packet information from theUSB-defined data packets and a command interpreter which is adapted tointerpret commands extracted from the USB-defined data packets intoactions for the at least one flash memory module; and (d) memorytechnology drivers, each adapted for execution by the USB controller toperform actions on a respective type of flash memory module; wherein theUSB controller is configured to activate a respective memory technologydriver within the flash memory device based on an identification of arespective type of the at least one flash memory module and theactivated memory technology driver is configured to perform actions onthe identified flash memory module.
 30. The USB flash memory deviceaccording to claim 29, wherein the USB controller further comprises afunctional interface adapted for processing token packets received fromthe USB-defined electrical and logical interface.
 31. A USB flash memorydevice comprising: a storage unit further comprising: at least one flashmemory module; a USB connector adapted for connection to a USB-definedbus according to a USB standard; and a USB controller adapted forconnecting the at least one flash memory module to the USB connector;wherein the USB controller is configured to support dual functionalityincluding USB functionality according to the USB standard and memoryfunctionality and control of the at least one flash memory module, theUSB functionality further including physical, logical and functionalinterfaces for sending and receiving USB-defined packets, includingUSB-defined data packets, via the USB connector and the USB-defined busto or from the host, and the memory functionality and control furtherincluding: a packet extractor to extract operation codes and logicaladdresses from the USB-defined data packets; a command interpreter whichis adapted to interpret the operation codes into commands correspondingto one of memory reads, writes and erases; and an address resolvermodule adapted for converting the logical addresses into correspondingphysical addresses in one or more of the at least one flash memorymodule.
 32. The USB flash memory device according to claim 31, whereinthe USB controller is an integrated circuit (IC).
 33. The USB flashmemory device according to claim 31, wherein the USB controller is anapplication-specific integration circuit (ASIC).
 34. The USB flashmemory device according to claim 31, wherein the memory functionalityand control further includes memory technology drivers (MTD), each MTDconfigured for recognizing a type of flash memory modules for which theMTD was designed and interacting with respective flash memory modules ofsaid type under the control of the USB controller, wherein the USBcontroller is configured to determine which distinct MTD to activate fora respective flash memory module based on type information of the flashmemory module.
 35. The USB flash memory device according to claim 31,wherein the at least one flash memory module includes a plurality offlash memory modules.
 36. The USB flash memory device according to claim31, wherein the USB connector is integrally formed with the storage unitand is able to protrude therefrom to facilitate connection to theUSB-defined bus.
 37. A method for communication between a storage unitand a host, wherein the storage unit includes: one or more flash memorymodules, a USB connector adapted for connection to a USB-defined busaccording to a USB standard, and a USB controller adapted for connectingthe one or more flash memory modules to the USB connector, the methodcomprising: receiving one or more incoming USB packets sent from thehost to the storage unit via the USB-defined bus; and in response to theone or more incoming USB packets, the USB controller performing memoryoperations to the one or more flash memory modules according to the oneor more incoming USB packets; generating one or more outgoing USBpackets according to results of performing the one or more operations;and sending the one or more outgoing USB packets to the host from thestorage unit via the USB-defined bus; wherein the USB controller isconfigured to support dual functionality including USB functionalityaccording to the USB standard and memory functionality and control ofthe one or more flash memory modules, the USB functionality furtherincluding physical, logical and functional interfaces for sending andreceiving USB packets via the USB connector and the USB-defined bus toor from the host, and the memory functionality and control furtherincluding: a packet extractor to extract operation codes and logicaladdresses from the incoming USB packets; a command interpreter which isadapted to interpret the operation codes into commands corresponding toone of the memory operations; and an address resolver module adapted forconverting the logical addresses into corresponding physical addressesin at least one of the one or more flash memory modules.
 38. The methodaccording to claim 37, wherein the USB controller is an integratedcircuit (IC).
 39. The method according to claim 37, wherein the USBcontroller is an application-specific integration circuit (ASIC). 40.The method according to claim 37, wherein the memory functionality andcontrol further includes memory technology drivers (MTD), each MTDconfigured for recognizing a type of flash memory modules for which theMTD was designed and interacting with respective flash memory modules ofsaid type under the control of the USB controller, wherein the USBcontroller is configured to determine which distinct MTD to activate fora respective flash memory module based on type information of the flashmemory module.
 41. The method according to claim 37, wherein the USBconnector is integrally formed with the storage unit and is able toprotrude therefrom to facilitate connection to the USB-defined bus.